The present application relates to the formation of back-end-of-line (BEOL) interconnect structures in integrated circuits and, more particularly to a method that provides enhanced protection to patterned features during a top oxide rounding process in the formation of the interconnect structures.
Back-end-of-line (BEOL) interconnect structures are used to electrically connect the device structures fabricated on the substrate during front-end-of-line (FEOL) processing. BEOL interconnect structures are routinely fabricated by damascene processes, such as a dual damascene process in which vias and trenches formed in a dielectric layer are filled with a conductive material using a single blanket deposition followed by planarization.
Trenches formed in the dielectric layer using conventional etching/hard mask removal processes typically have sharp, squared-off top corners which cause the formation of defects, such as voids, within the trenches when filling the trenches with the conductive material. One method to mitigate this filling problem is to round the top corners of the trenches using a fluorocarbon-based plasma etch to allow a more uniform deposition of the conductive material. However, top corner rounding (TCR) with conventional fluorocarbon-based plasma etch chemistries normally results in undesirable effects, such as increased via critical dimension (CD) and trench over-etching, making it difficult to maintain trench and via profiles. As such, a method that allows a better preservation of patterned feature profile during a TCR process is needed.